1. Field of the Invention
The present invention relates to a semiconductor integrated circuit (IC) memory (referred to as "semiconductor memory device" hereinafter), and more particularly to a semiconductor memory device which may be used by switching in a one-bit input and output mode as well as in a multi-bit input and output mode with the shared use of a single chip, and enables memory write masking.
2. Description of the Prior Art
The majority of the semiconductor memory devices in the early days had the one-bit input and output mode configuration which input or output only one-bit data primarily for the purpose of suppressing an increase in the number of IC pins. However, mass storage has been accelerated as the application field of the semiconductor memory devices has expanded with the improvement in the level of integration, and devices have been developed with multi-bit input and output mode configuration which simultaneously inputs or outputs data with a plurality of bits. In such a semiconductor memory device, the same address terminal is multiply used in time series for a row address signal and for a column address signal, and the same terminal is used for data input and for data output by switching between them.
Now, under the semiconductor development race which has become increasingly vehement in recent years, it is becoming general to adopt a technique in which there is arranged a circuit necessary for both one-bit input and output mode configuration (abbreviated as one-bit configuration hereinafter) and multi-bit input and output mode configuration (abbreviated as multi-bit configuration hereinafter), and these configurations are changed by switching between them with a bonding or a mask. It is to be noted that even for a semiconductor memory device to be used in the one-bit configuration such a technique is effective at the time of testing in reducing the test time, which has been recognized as a problem that accompanies the advancement in the level of integration, by giving the device the multi-bit configuration. In a semiconductor memory device of this technique the multi-bit configuration is dealt with by providing write amplifiers in a number at least equal to that of the bits that can be written simultaneously, and a selector that selects one write amplifier based on the address signals is provided to handle the case of one-bit configuration.
In the semiconductor memory devices of the multi-bit configuration, such as in the case used as a RAM for an image in CRT or the like, there arise many instances in which there is required a memory write masking function which can invalidate the information writing to, that is, which can write mask every one of the bits. Conventionally, memory write masking is executed by providing write mask data input circuits corresponding to the respective write amplifiers that input write mask data from data input terminals and supply them to write amplifiers at the time of multi-bit configuration, and a write mask decoder which decodes the address signals that are identical to the address signals that are supplied to the selector, and supplies a write amplifier enable signal to one of the write amplifiers only at the time of one-bit configuration. In other words, write masking is executed by inputting write mask data that are not subjected to address selection within the semiconductor memory device and a write amplifier enable signal that is subjected to address selection within the semiconductor memory device, to the write amplifiers.
Accordingly, there are required a large number of control signal lines for write amplifiers, and from the layout design for the semiconductor memory devices the write amplifiers are arranged substantially removed from the write mask data input circuits and the write mask decoder. Because of this, the wiring area becomes large which has been a serious obstacle to the miniaturization effort for the semiconductor memory device. Moreover, an increase in the wiring area leads to an increase in the parasitic capacitance which also gives rise to a problem in conjunction with the effort for enhancing the operational performance.